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From: Tejas Bhatt
Date: Saturday, April 01, 2006
Time: 06:59 AM
TEJAS H. BHATT 1255, University Avenue Apt # 321, Sacramento, CA 95825 Email: bhatt_tejas@hotmail.com Phone: 916-595-7289 (M) OBJECTIVE: Seeking an intern/Co-Op/Full-time position in field of VLSI Design/Testing/Verification which will utilize and enhance my skills. EDUCATION: Master of Science in Electrical Engineering, California State University, Sacramento. GPA: 3.3 Dec ‘2006 Bachelor of Engineering in Electrical Engineering, V.V.P. Engineering College, India. GPA: 3.69 June ‘2002 COURSE WORK: CMOS and VLSI VLSI Design and IC Testing Advanced Logic Design C Programming Microprocessors (8085) Hierarchical Digital Design Methodology Applied Electronics Advance Electronics Circuits Micro-Computer System Design I SKILLS: Hardware Descriptive Languages: VHDL, Verilog Design Tools: L-edit, Max-plus II, Microsoft Visio Programming Languages: C, Java, MATLAB® Operating Systems: Windows 98/2000/XP, Dos, UNIX, Mac OS X Communication and Management: • Have excellent organizational, planning & coordination skills developed through work experience and professional activities. • Excellent Interpersonal skills, leadership and teamwork qualities enhanced by group projects and co-curricular activities. • Highly Self-motivated, result oriented, quick learner, self starter. Possess excellent analytical thinking and problem solving skills. • Able to think and handle on job situation independently. PROJECTS AND PAPER PRESENTATIONS: VLSI Manufacturing Techniques: • Prepared a Research paper on Semiconductor Packages, Fall 04. This paper deals with evolution of packages in IC industry and its different types like Dual Inline Package (DIP), CSP, QFP etc. Also it talks about new technologies in the field like Wafer Level Packaging, 3-D CSP, Flip Chip. Advanced Logic Design Projects: • Designed a project to display data on LCD. Displayed data like casino dice so that LCD would display random data from 1 to 6 at the switch press. Designed the project using complex VHDL techniques and also displayed output on Logic Analyzer in various timing modes. Implemented this design on FPGA proto-board. • Designed a door lock system using VHDL. A certain sequence of input must be given for the door lock to open. CMOS and VLSI Project: • Member of two persons’ team that designed and laid out a 3 bit shift register. L-edit was used for layout of this project. Micro-Computer System Design 1: • Designed a bus steering control logic circuitry for an Intel 386 microprocessor and ISA Bus running at 8.333 MHz, compatible, on a limited basis, with the PC AT (ISA) architecture. The design is developed using Intel 80386DX-8MhZ microprocessor (32-address lines, 32 data lines). The project was designed in Verilog. • Designed a PCI 32bit memory card, with four 128K*8 EPROM using Verilog. • Presented a technical paper in a team of Two on HyperTransport™ Technology. It discussed about the architecture of the HyperTransport™ Technology and its applications. Hierarchical Digital Design Methodology: • Designed a Floating point Single Precision Multiplication system with pipe lining feature, using RTL logic, Spring 05. Tool used was Verilog. Also designed a test-bench for the same and synthesized and optimized the design for timing and area constraints. Undergraduate Final Project: Transistor Curve Tracer: • Designed and fabricated a Transistor Curve Tracer on a PCB board. The input of this device is connected to a transistor and output to a CRO. The Transistor Curve Tracer shows the input and output characteristics of transistor on the CRO, and a switch is used to select between these two characteristics. Also developed the circuit to use it with various power electronics devices like diode, JFET, MosFET etc. and controlled it with another switch. WORK EXPERIENCE: System Support Assistant Engineering Computer Lab 02/04 -Present • Responsible for assisting Network Administrators to handle a large cluster of computers systems. • Maintaining Faculty computer systems and their problems related to printers, hard drives, memory, software and network related problems with wireless networks, Virtual private networks etc Junior Engineer Karnavati Engineering Ltd. 09/03- 12/03 Responsible for documentation and co-ordination for all the departments of the organization for ISO 9001:2000 and technical documentation of company’s products as per CE standards.
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