4.6 Yrs Exp. in ASIC / VLSI Design - Verilog, RTL, Custom IC Layout, Physical Veirifcation - DRC / LVS / ERC / DFM - EM / LUP / ANT, Digital Design, BFM, Perl, Tcl, Spice simulation, Virtuoso, Calibre, Hercules, modelsim, hspice / hsim / spectre, cmos, characterization, fpga

From: Ravi Prakash, Secured & permanent is highest priority condition.
Remote Name: 117.200.163.68
Date: Friday, January 23, 2009
Time: 12:35 AM

Resume

4.6 Years Overall Semiconductor VLSI/ASIC Development Related Technical Exposure in following areas: • Digital Semi-Custom ASIC’s Std. Cell Layout Modifications & Physical Verification – DRC/LVS/DFM – EM/LUP bug fixing. • ASIC - Custom Layout & Physical Verification – DRC/LVS/DFM – EM/LUP/ANT bug fixing in layouts. • Digital Logic Design, Structural & RTL HDL Coding (Verilog) For Synthesis, HDL Simulation, Behavioural Specs Conversion into BFM/Test bench for Verification of specs logic given in specs document & Logic Equivalence check in Verilog. • Digital ASIC's Standard Cells – Post Layout Spice Simulation, Characterization, Cell Library Validation. Aim : Looking for secured & permanent job in digital ASIC / VLSI / FPGA semiconductor domain. EMPLOYMENT HISTORY: (IN CHRONOLOGICAL ORDER) Present Status: Not working anywhere. 01/2008 – 11/2008 Designation: Design Engineer - FE. Company: Small R&D Start Up in VLSI / FPGA. • To Design & Verify the USB 2.0 standard system micro-architecture based communication protocols & host/device digital module designs based on behavior in specs document given. • Digital Logic Design (Micro-architecture), HDL coding & verification of standard USB 2.0 System Signal interface protocol, standard data transfer interface protocol, standard USB data format & transfer logic for ISO/Bulk/Control/Interrupt data transactions (token/setup, data, handshake stages). Roles involved: • Understanding the Functional/Behavioural specs document, Digital logic design (micro architecture design) for precision coding for synthesis, FSM for digital sequential logic design whenever needed. • Logic Equivalency: Conversion of behaviour of specs into behavioural verilog BFM for comparison with RTL/Integrated (structural mapped) code design behaviour through digital simulation, writing test bench, verilog tasks for monitors & checkers for digital design logic bug tracking & reporting. • RTL & structural mapped (RTL integration on cell/block/module level) coding for synthesis in verilog from bottom to top level of modules (in micro-architecture document available). • RTL simulation & test bench for giving stimulus to DUT as per spec behavior given in document available. • Lint checks: Language coding syntaxes & format checks by verilogHDL compiler integrated with modelsim. • Functional Coverage: Behavioral coding in verilogHDL to check the coverage of all possible input logical combinations & states in digital logic designs. • Test bench/verification automation in verilog for sending stimulus to DUT in verilogHDL, writing assertions, monitors/checker tasks to check & report logical/behavioral bugs, logical state sequence test in sequential designs/FSMs, task/function & UDP modeling for BFM or to check the communication between modules & user arguments. • Custom static timing analysis for design through writing verilog timing test benches for set-up/hold/recovery/ frequency/period/ propagation delays/intrinsic delays/race conditions/multiple driver/clock & net skews/trans receiver module communication data loss & cross domain/multiple frequency domain mismatches…etc. • Path delay approximations & BFM development for reporting path delays in various logic topologies for selection of best topologies for high speed or area constrained or low power effort calculation based methodology on MOS level for various load capacitances/drive strengths & technologies widely used for std cell library design for optimization of micro-architecture if sufficient time & pay for doing R&D is given to work on customized levels or having the specific target technology liberty model for proper approximations & better results rather than only doing on superficial digital design/coding irrespective of what technology has to be mapped for synthesis of design like in most of the project outsourcing shops running for making money. Tools used includes are Mentor's ModelSim/QuestaSim (hdl compiler & digital simulator, code coverage tool, static waveform viewer & gate logic viewer), Xilinx's ISE tool (XST – FPGA design synthesis, design constraint editor, implementation, fitter, floorplanner, pin assignment editor, APR, timing analysis/post routing simulation & bit stream generator for code download in FPGA & JTAG/boundary scan) & Xilinx's FPGA – Spartan III. 07/2007 – 12/2007 Designation: Sr. Standard Cell Design Engineer –E2, IDC BLR/HYD. Company: Conexant Systems Pvt. Ltd. (Nasdaq: CNXT), Hyderabad/Bangalore. Company URL: (http://Conexant.com • Brought in by company in Foundation IP BU to support a new design team tasked with developing standard cell library for company’s communication CMOS ASIC products (set top box & internet communication modem ICs). • To fit the new DFM constraints, fixing the physical verification bugs in technology migrated cell layouts from 11 track to 9 track area constrained library sent us for modifications for set top box conexant’s CMOS process ICs on 65nm GP TSMC technology constraints according to respective standard cell DRM, manufacturing/fabrication grid/etching resolution of 0.005 micron, scalable drawing grid of 0.2 micron. Roles involved: • Collection of cell library complaints from chip integration/physical design & STA teams. • Estimation of average aspect ratio of standard cells required in library & standard hight of cells on the basis of number of cells in the synthesis report of frontend logic of top level digital core architecture & the aspect ratio of the total area available in chip floorplan for digital core fitting, DRC & DFM spacing rules of metal1 layer in technology to be used to take under consideration for estimation of full digital core fitting in floorplan. Constraint to focus on area reduction from 11 track to 9 track cell heigth in 65nm TSMC technology standard DRM. • Checking & fixing physical verification bugs (drc/lvs/em/lup) in library cell layout views using calibre tool. • Modifications & new cell layout template development for missing/incorrect technology migrated cells & new cell drives, other layer size modifications (using cadence virtuoso) asked by library manager to do upon inputs given by PDK library team on quality & relaibity of cells in terms of target technology/present product qualification necessities/failures encountered. • Layout RC extraction (calibreRCX) & spice bench (hspice/spectre) for spice simulations for documenting dynamic/relative delay arcs. • Dynamic & Static Cell Timing QA (Through spice simulations – hspice/spectre): Checking rise & fall time dynamic slews of input & output cell pins, input to output combo delays (relative/static), clocked cell’s (scan/normal flip-flops) internal timings for early/delayed clock arrivals, un-optimized clock to q & input/output clock & data buffer delays inside flip flops, internal balancing of clock net skews...etc, circuit sizing for getting steeper & small linear region in outputs of data & clock buffers to reduce the probability of setup/hold violations due to unrecognized digital o/p levels (not either below VOL(max) or above VOH(min) levels). • Sending cells, cell modified area report after modifications & physical verification to library manager for cell IR drop (cadence-Voltage Storm) & SI aware delay report generation (using Cadence-CelticNDS) by QA team & modification of layout cells by us as per bugs reported by them or by celtic reports sent by them for relevant cell layout modification to improve cell delay responses. • Running horizontal abutment & half drc (cell boundry) check for quality assurance of P&R & fixing boundary/abutment bugs on all cells abutted by running scripts (given by software/EDA support team). • Sending cells for lib characterization to run it on all cells & for final views, model generation & their validation to QA team. • Collection of cells assigned to junior engineers to send it to library manager after doing abutment/boundary check on all cells collectively & Supporting new college graduates in operating virtuoso & calibre tool usage for cell layout modifications & interpretation of drc/lvs/em/lup violations reported by calibre tool to fix in cell layout views to cope up with work. Tools used includes are Cadence’s Virtuoso XL/LE/Turbo (Custom Cell Layout views of std cells), Synopsys’s H-Spice/Cadence’s Spectre (for spice simulation), Mentor’s Calibre (for physical verification & Calibre RCX for LPE), Cadence – CelticNDS (for cell level SI/xtalk/noise aware delay calculation report from layout RC netlist), Cadence’s Composer (for schematic views of circuits). 11/2006 – 06/2007 Analog IC Layout Engineer, ODC Backend VLSI, Bangalore. Company: Tata Consultancy Services Limited (TCSL), India. Company URL: (http://www.tcs.com • Involved in Analog layout & physical verification of a photosensitive ASIC for company’s digital camera product on TLM CMOS process, 130nm TSMC technology constraints according to respective analog IC DRM: Roles Involved: • Collection & understanding the schematic circuit to be converted in to layout & layout constraints given by circuit design team. • Analog layout drawing (p-cell manual placement & routing) of the circuits in schematics according to their sizes mentioned in schematics & checking/fixing layouts for physical verification (drc/lvs/lup/em) with virtual connection if required for higher hierarchy connection assumption. • Manual matching of devices, layer notches/corners, interconnect alignment for uniform etching & prevention of main device area etching, capacitors & resistors placement, cross/lateral coupling shielding, cell to block level bottom to top level integration of instances/cells, manual P&R, physical verification on top level hierarchy again. • Cell aspect ratios through top level Macro/Block floor plan optimum placement of each cell with physical design team, power routing layer decisions & preferences for better couplings to ground/power & less IR drops & latch up/parasitic diode substrate leakage currents, hierarchical planning of multiple layers for minimum cross couplings & prevention of electro migration failures & defects in real time in silicon. • Cell level – layout (manual p-cell integration) & physical verification – DRC/LVS/DFM – Electro-migration, Latch-up, Antenna violations check & fixing, signal & device shielding for reducing the lateral & cross couplings, dummy signal layer & dummy device insertion for prevention of lateral couplings & over etching/undercut of critical physical device regions. Component (transistor/resistor/capacitor p-cells) sizing according to the circuit sizing information in schematics views, their placement & routing with matching constraints taken in care using automated CDFII features/PDK available in support with virtuoso tool. • Block level integration of cells (manual placement & routing with matching interconnect/notch/corner mis-alignment to prevent over-etching/undercut manufacturing output yield loss & electro-migration failures in post silicon RT self heating & burn outs in silicon, matched stack/component orientation, matched current flow directions for uniform charge distribution, charge density/potential gradient uniformity in layouts, required signal/device shielding & antenna preventive measures to reduce the direct gate exposure area to the external charges & accumulation of charges under gate regions.) & physical verification for overall work & fixing before checking in for review for circuit design & characterization team. • Taking part in layout reviews by analog frontend designers & figuring out the mismatches in layouts for corrections. Tools used include Cadence Virtuoso ADE (for Custom Layout), Mentor’s Calibre (for Physical Verification). 02/2006 – 07/2006 Standard Cell Library Design Engineer , IDC Bangalore. Company: Microchip Technology Inc. (Nasdaq: MCHP)(AZ,US/Bangalore, IND). Company URL: (http://www.Microchip.com • Involved in supporting newly started library development department for high voltage, high speed & low leakage std cell libraries/IPs - standard cell modifications, cell characterization & validation for commercial 8/16 bit microcontrollers ASIC cell libraries of 180nm (for high speed ASIC library) & 250nm (for high voltage/low leakage ASIC library) CMOS process TSMC HS & HV used in most of the automobile industries for automatic electro-mechanical robotic controls, manufacturing/fab grid/etching resolution of 0.005 micron & drawing grid of 0.2 micron: Roles Involved: • Collection of cell layouts from layout engineer for parasitic extraction & characterization of cell layout net-lists. • Creation of MTB/Nano-Char tool environment & input files to run characterization & validation on extracted net-lists for input/output capacitance, delays & power arcs on various PVT corners/OCVs. • Cell hdl model validation & writing test bench in verilog for timing & functional validation of cell hdl models annotated with actual path delays specified in verilog (writing perl scripts for delay data extraction from delay data arcs acquired from extracted layout spice net-lists (.del metrics files) & appending with functional verilog hdl models (.v) & generating respective cell verilog timing models for timing simulations) upon spice simulations on parasitic net-lists of cells to acquire delay arcs) with functional hdl model for timing simulations. • Liberty model (.lib) validation & various view generation for porting cell timing/power/layout views/hdl models in ASIC EDA integration Flow to enable RTL-GDS tasks, timing closure (STA) & power compilation on top level modules for microchip’s internal full chip integration customers (front end implementation (RTL-Net-list/Synthesis/Gate level validation teams) & physical design (backend layout/P&R/Net-list-GDS teams) & sign off (pre-silicon/post routed net-list timing & power validation teams)). Tools used include Cadence’s Schematic composer, Cadence’s Virtuoso LE/Turbo, Synopsys’s Hercules (Physical Verification), Synopsys’s H-spice/H-Sim, Synopsys’s NanoChar/MTB (for Cell Characterization & Validation of timing & power arcs, .lib (library’s PVT Corners/OCV cell trend curves/slew matrix documentation) & cell hdl model generation), Mentor Graphic’s – model sim (digital hdl compiler, digital simulator, code coverage tool & wave form viewer). 06/2004 – 01/2006 Design Engineer – VLSI Applications, Pune. Company: Ni Logic Pvt. Ltd. Pune. Company URL: (www.ni2designs.com) • Roles involved in Digital design for VLSI front end, RTL/Structural/Behavioral Coding for design entry & digital gate level simulation, FPGA synthesis & small system application development using FPGA protoboards/emulation boards, maintainence of hdl codes for respective FPGA application examples for maintenance of FAE kit. Roles Involved: • Digital Logic Design, FSM for sequential state machines if required for precision coding for design synthesis. • Path delay approximations & BFM development for reporting path delays in various topologies without using synthesis tool or standard cell library attached for selection of best topologies for high speed/freq. designs based on progressive sizing methodology on MOS level for various load capacitances/drive strengths & technologies. • Lint check: HDL language syntax/format checks & fixes reported by hdl compiler while code compilation. • Design for Synthesis: RTL coding for FPGA synthesis in Verilog/VHDL. • Functional Coverage: Behavioural Coding in Verilog/VHDL to check the coverage of all possible input logical combinations & states in digital logic designs. • Logic Equivalency: Conversion of behavior in specs into BFM for comparison with RTL/Structural Coded design behavioral through digital simulation. • RTL design synthesis. • Monitors & Checkers for verification bug reporting, monitoring & tracking design logic bugs. • Custom static timing analysis on gate level net-lists through GLS using test benches for design in verilog for set-up/hold/recovery/ frequency/period/race conditions/multiple driver/clock & net skews/trans receiver module communication data loss & cross domain/multiple frequency domain mismatches…etc. • FPGA Design: RTL design for Xilinx & Altera FPGA synthesis & on board RT application module architectures, entity functional & configuration constraints in their respective specs given. • Gate & circuit level custom VLSI design tool applications support on digital RTL level to circuit level digital symmetric cmos logic circuits, spice test benches for functional simulation & characterization on physical implemented circuits (layouts) on parasitic net-lists, physical layout development & their verification tools in built. Taken part in development & maintainence of FPGA Demo/Example Applications/FPGA Protoboard Applications: Application test case development for FPGA proto-boards for Dot matrix (pixel based) LCD, Matrix keypad (Simple calculator & data display), Seven segment led displays, ADC (3 line analogue input/8 bit sampled output)/DAC (4 bit digital input/2 line analogue output) applications (analogue data acquisition, A/D conversion, digital data processing (PWM/sampling, data addition/subtraction & any digital combinational/sequential logic operations…etc) & displays on seven segment led displays & matrix LCD displays), Serial port interfacing (Serial digital data acquisition (in distributed RAM (LUTs & Flip Flop based logic in FPGA) or in external/onboard EPROM/RAM), digital processing & onboard displays or to DAC & analyzing o/p on CRO), on board EPROM/RAM memory interfacing & Read/Write operations (for field applications/backup/bulk data storage purposes), Led/switch programming on board. EDA tools used are Xilinx's ISE, Altera's Quartus II, Mentor's Leonardo Spectrum, Modelsim & FPGA proto boards. MISCELLANEOUS (JOB CONCERNED EDA TOOLS ARE MENTIOEND BELOW RESPECTIVE JD’S) Programming/Scripting Languages: Basic of Perl, Tcl, Shell/Unix scripting. Hardware Description Languages: VerilogHDL & little bit of VHDL. Working OS Platforms: workable on Linux, Fedora, Sun Solaris & Windows: 98/2000/Me/NT/XP/Vista. Others: Basic awareness to simple website development using MS frontpage & manual publishing/editing html pages, SEO/page ranking/www publishing/article submission, web traffic booster techniques & online traffic enhancer programs, personal tool kit for website development for e-commerce bussiness applications…etc, basic Perl CGI scripting supporting web automation of web page transition & internet fraud security for host site contents, B2B, internet affiliate marketing & advertisement, simple product web catalogue/photo galleries, pay per click (ppc)/view ads (through google adword campaignes), google adsense…etc. • Aware of ASIC design flows & processes involved. • Aware of yield practical dependencies undercut/over etching on layout uniformity, interconnect alignment, unmatched instance/cell/block sizes, cell abutments in various orientations. • Aware of practical awareness of post silicon reliability of chip on electro-migration in metal layers, their order of precedence in terms of resistance offered by them, parasitic latch-up structures, noise introduction through open gates/antennas, parasitic couplings & static losses/drops in power, timing mismatches due to skews in interconnects, clock routings, physical block delays appearing in critical paths. • Can visualize up to some extent, virtuoso of IC stack to understand the issue in practical way as it may happen in real time run after silicon. Education: • Post Graduate 1.6 Year Diploma (MS Equivalent) in VLSI Design & Microelectronics Engg. - 2003-2004 • B.E Electronics (Four Year Full Time Degree) – 1999-2003

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